System LSIs for Digital Broadcasting Applications

2.1 Target applications

The target applications of VASA and ISIL are shown in Fig. 2. VASA is for professional use and is used for contribution transmission (original material transmission before authoring) (explained in section 3.1)), while ISIL is for consumers and prosumers and is used for low-power, inexpensive information appliances. The figure shows resolution and frame rate as a measure of codec performance. VASA covers the entire figure but mainly supports 1080i (1080 lines of vertical resolution with interlaced scanning) for half-duplex processing (either encoding or decoding) in a single chip and super-high-definition beyond HDTV in multiple chips. In contrast, ISIL covers under-720/30p (30p: 30 frames per second with progressive scanning) encoding and mainly supports full-duplex 480i/480p; it supports 1080i only for decoding.

Fig. 2. Target applications of VASA and ISIL.

2.2 VASA hardware

VASA consists of three encoding cores (E-COREs), a decoding core (D-CORE), a multiplexer/demultiplexer core (MDX), a video interface/display (VIF/DISP), a watermark (WMK) module, a top-chip RISC (reduced instruction set computer) processor (TRISC), and several dedicated application-specific hardware modules with multichip data transfer (MDT) and a memory interface (MIF) for a hierarchical flexible communication scheme for high-performance data transfer [9]. VASA implements MPEG-2 video and system codecs with generic audio codec interfaces. It provides not only an MPEG-2 422P@HL codec but also large-scale processing beyond the HDTV level for digital cinema and multiview/multiangle live TV applications when a multichip configuration is used.

VASA's hierarchical flexible communication for the control and data of parallel encoding is based on macroblock pipelined schemes in each parallel encoding core and between cores with a two-level memory hierarchy for the intra- and inter-cores. All application-specific hardware modules and cores dedicated to the MPEG-2 implementation are connected to both a hierarchical CPU bus for small amounts of control data and to a hierarchical system bus for huge amounts of picture data. The flexible communication in a chip is performed by the TRISC and MIF, while the flexible communication in a core is performed by video RISCs (VRISCs) and data interfaces (DIFs). The MIF controls the external DDR-SDRAMs (double data rate synchronous dynamic random access memories) in order to minimize their input/output rate. The inter-chip data transfer through the MDT enables the VASA chips to use the data on other VASA chips for a multichip configuration.

2.3 VASA software

The VASA software consists of three layers: the hardware layer, the hardware control layer, and the function layer [9]. The hardware control layer is TRISC and VRISC software for controlling the VASA hardware, while the function layer is TRISC software for handling MPEG-2 common basic functions and customized functions for each user. Communication between the hardware layer and the hardware control layer is accomplished via the hardware/software interface in the VASA hardware. Communication between the hardware control layer and the function layer is accomplished via the common function interface in TRISC. Communication between MPEG-2 common basic functions and the user customized functions is carried out via the customized function interface. This software hierarchy not only completely frees users from the tedious task of controlling VASA hardware using the low-level hardware/software interface and the difficulty of handling MPEG-2 common basic functions, but also provides a simple programming interface as a custom function.

2.4 Chip characteristics of VASA and ISIL

The physical features of the fabricated VASA and ISIL LSIs are shown in Fig. 3. VASA integrates 61.4 million transistors in a 14.0 mm × 14.0 mm chip using 0.13-µm 8-level metal CMOS (complementary metal oxide semiconductor) technology. ISIL integrates 30.7 million transistors in a 10.0 mm × 10.0 mm chip using 0.13-µm 7-level metal CMOS technology. Microphotographs of these LSIs are also shown in Fig. 3. As can be seen, VASA integrates a TRISC, three E-COREs, a D-CORE, an MDX, a VIF/DISP, a WMK, an MDT, and an MIF, while ISIL integrates a TRISC, a single E-CORE, a D-CORE, an MDX, a frame rate converter (FRC), a digital signal processor (DSP), and two MIFs. All the logic circuits on these chips were constructed using only standard cells in order to shorten the design time. Hard macros were not used except for the memories and the TRISC.

Fig. 3. Microphotograph and physical features of VASA (left) and ISIL (right).

3.1 Broadcasting mechanism and digital television network in Japan

The television broadcasting mechanism and the television network system [10] in Japan are shown in Fig. 4. The typical ways of transmitting television broadcasting are (1) contribution transmission, (2) interruption transmission, and (3) final distribution transmission. Here, contribution means material before authoring. This is visual contents generated at the key TV station and the local TV stations. Interruption transmission means a temporarily setup contribution. This is visual contents generated outside the stations (such as at live events) using an outside broadcast van. Both contribution and interruption are visual contents before authoring, so the bitrates used are higher than those used for distribution. Distribution means the final-output contents for end-users after authoring; it uses a lower bitrate.

Fig. 4. TV broadcasting mechanism and TV network service in Japan [10].

As shown in Fig. 5, the digital television network [10] offered by NTT Communications (NTT-COM) in Japan consists of an optical fiber loop line covering the whole country, access lines between edge stations (NTT-COM buildings) and broadcast stations, and an operations center (NTT-COM) that controls the network operations of routing traffic and sharing lines. The digital television network is based on a highly reliable ATM (asynchronous transfer mode) network with a redundant and fault tolerant design for a seamless error-free environment.

Fig. 5. Digital terrestrial broadcasting network [10].

3.2 High-end codec systems for broadcasting infrastructure

(1) Contribution transmission system

The VASA module (15.8 cm × 7.2 cm), which contains one VASA LSI and four DDR-SDRAMs, and NTT-COM's contribution transmission codec systems [10] that use this VASA module for the digital television network are shown in Fig. 6. This codec system implements an MPEG-2 422P@HL codec for contribution transmission with ATM transmission capability in a “1U-full-rack-sized space” thanks to VASA's compact, low-power, and reliable design. This codec system also provides flexible transcoding capability for changing the bitrate during runtime from the high-bitrate short-GOP for contribution to the low-bitrate long-GOP for distribution (GOP: group of pictures). A large number of these high-end MPEG-2 codec systems have already been put into practical operation in the digital television network for Japanese digital terrestrial broadcasting, which started in December 2003.

Fig. 6. HDTV codec system for contribution transmission of digital terrestrial broadcasting [10].

(2) Interruption transmission system

Using the VASA module, NHK and NTT-COM jointly produced the world's smallest MPEG-2 HDTV codec module, which contains one VASA and a digital field pickup unit [11], which is a portable microwave link for interruption transmission, as shown in Fig. 7. This codec system implements an MPEG-2 422P@HL codec for interruption transmission capability in a post-card-sized area. Thanks to VASA, the size and power consumption were drastically reduced to one tenth of previous implementations. This compact codec system will accelerate the portability of HDTV content creation and circulation. A large number of these compact high-end MPEG-2 codec systems have also been in practical operation in the digital television network for Japanese digital terrestrial broadcasting since December 2003.

Fig. 7. Very compact HDTV codec system for digital field pickup unit [11].

(3) Distribution transmission system

For contribution transmission, it is important to provide high-quality, low-delay transmission with a high bitrate, which is implemented as simple one-pass encoding. On the other hand, distribution transmission can use a lower bitrate (higher compression ratio) and still maintain end-user quality. VASA is used not only in contribution transmission for simple one-pass encoding, but also in distribution transmission for advanced and more complicated two-pass (or tandem) encoding using recoding information.

The architecture of a high-compression two-pass (tandem) transport stream (TS) output encoder system [12] with VASA for distribution transmission is shown in Fig. 8. This encoder system performs realtime encoding in two passes: first, recoding (previous encoding) information is extracted by pre-analysis encoding; then, real encoding is performed using this recoding information. As a result, a higher compression ratio is achieved. Another advanced encoder, called the TS-switcher (Fig. 9) [13], combines transcoding and tandem encoding for seamless blending of the transport stream from the key station and the transport stream from a local station using recoding information. These advanced high-end VASA-based encoder systems have also been used in practical operations by NHK and many commercial broadcasters in the digital television network for Japanese digital terrestrial broadcasting since December 2003.

Fig. 8. HDTV encoder system that outputs a high-compression transport stream for digital terrestrial broadcasting [12].

Fig. 9. Seamless TS-switcher for digital terrestrial broadcasting [13].

(4) Super-high-resolution future codec system beyond HDTV-level

Multichip configurations of VASA make it easy to implement future high-quality, high-resolution visual applications beyond the HDTV-level, such as super-high-resolution (SHR) TV (future TV) or digital cinema and/or multiview and multiangle live TV (for sporting or music events). The “1U-full-rack sized” SHR codec system [14] with VASA, which can handle 4000 × 2000 pixels (termed 4K), far exceeding the HDTV-level of 1920 × 1080, is shown in Fig. 10. The SHR picture is split into four HDTV images and allocated to several 422P@HL encoders including the VASA chip. After parallel encoding on the VASA multichip configuration, a transport stream of the original SHR picture is output from the bottom of the VASA chip. The left figure in Fig. 10 shows Hikari Net Live: the Saito-Kinen orchestra (two HDTV images) and the bottom figure in Fig. 10 shows a public viewing (three HDTV images). Live music and sports events like these in the SHR TV format will become a popular form of digital multimedia entertainment in the near future.

Fig. 10. Future super-high-resolution (SHR) codec system.

3.3 Peripheral codec systems for broadcasting infrastructure

The advent of compact consumer/prosumer HDTV video cameras [15] with HDV compliance and embedded small modules [16] is accelerating changes in digital TV content creation and circulation. These days, it is necessary to provide more attractive and dynamic images. The many ISIL-embedded mobile systems, wireless cameras, and module systems have recently made possible a lot of popular and attractive digital TV visual contents and outdoor scenes such as car and yacht races; soccer, baseball, and golf games; orchestral and operatic music events; and athletics events such as the recent Athens Olympic Games.